Raza Microelectronics, Inc. BSDL for the RMI Alchemy™ Au1000™ Processor *************************************************************************************************************** Disclaimer: This file contains the latest information about the BSDL files for the Alchemy Au1000 processor. RMI does not assume any responsibility nor guarrantee the use of any circuitry or software described. No circuit or software patent licenses are implied and RMI reserves the right at any time without notice to change said software, circuitry, or specifications. ------------------------------------------------------------------------------------------------------------------------- -- AU1000.bsdl - IEEE 1149.1 Boundary Scan Description -- -- -- -- DISCLAIMER: This information is for modeling purposes only, and is -- -- not guaranteed. This information may contain technical inaccuracies -- -- or typographical errors. Alchemy Semiconductor Inc. reserves the right -- -- to withdraw this information at any time without notice. -- -- Copyright 2001 Alchemy Semiconductor Inc., All rights reserved -- -- -- -- ELECTRONICALLY VERIFIED -- -- Rev. 1.0 08/21/2002 -- -- Rev. 1.1 12/04/2002 -- -- Rev. 1.2 04/27/2004 -- -- Rev. 1.2 04/27/2004 -- -- 1. Changed SDCLK vector to out instead of inout--documentation lists -- -- these pins as output-only -- -- Rev. 1.1 12/04/2002 -- -- 1. Removed the attribute PORT_GROUPING for USB pins, it is not needed. -- -- Each pins has its own boundary cell: -- -- attribute PORT_GROUPING of AU1000 : entity is -- -- "Differential_Voltage ( (USBHP, USBHM), (USBDP, USBDM) )"; -- ----------------------------------------------------------------------------- entity AU1000 is --- Generic Parameter (ref B.8.2) --- generic (PHYSICAL_PIN_MAP: string:= "BGA_22x22"); --- Logical Port Description (ref B.8.3) --- port( SDA : buffer bit_vector (0 to 12); SDBA : buffer bit_vector (0 to 1); SDD : inout bit_vector (0 to 31); SDQM : buffer bit_vector (0 to 3); SDRAS_N : buffer bit; SDCAS_N : buffer bit; SDWE_N : buffer bit; SDCLK : out bit_vector (0 to 2); SDCS_N : buffer bit_vector (0 to 2); SDCKE : buffer bit; RAD : inout bit_vector (0 to 31); RD : inout bit_vector (0 to 31); RBEN_N : inout bit_vector (0 to 3); RWE_N : inout bit; ROE_N : inout bit; RCE_N : inout bit_vector (0 to 3); PREG_N : inout bit; PCE_N : inout bit_vector (0 to 1); POE_N : inout bit; PWE_N : inout bit; PIOR_N : inout bit; PIOW_N : inout bit; PWAIT_N : in bit; PIOS16_N : in bit; LCLK : buffer bit; LWAIT_N : in bit; LRD_N : inout bit_vector (0 to 1); LWR_N : inout bit_vector (0 to 1); EWAIT_N : in bit; USBHM : inout bit; USBHP : inout bit; USBDM : inout bit; USBDP : inout bit; S0DOUT : inout bit; -- MUX w/GPIO16 S0DIN : in bit; S0CLK : inout bit; -- MUX w/GPIO17 S0DEN : inout bit; -- MUX w/GPIO18 ACSYNC : inout bit; -- MUX w/S1DOUT ACBCLK : in bit; -- MUX w/S1DIN ACDO : inout bit; -- MUX w/S1CLK ACDI : in bit; ACRST : inout bit; -- MUX w/S1DEN IRDATX : inout bit; -- MUX w/GPIO19 IRDARX : in bit; U0TXD : inout bit; -- MUX w/GPIO20 U1TXD : inout bit; -- MUX w/GPIO21 U2TXD : inout bit; -- MUX w/GPIO22 U3TXD : inout bit; -- MUX w/GPIO23 U0RXD : in bit; U1RXD : in bit; U2RXD : in bit; U3RXD : in bit; N1TXCLK : in bit; N1TXEN : inout bit; N1TXD : inout bit_vector (0 to 3); N1RXCLK : in bit; N1RXDV : in bit; N1RXD : in bit_vector (0 to 3); N1CRS : in bit; N1COL : in bit; N1MDC : inout bit; N1MDIO : inout bit; N2TXCLK : in bit; N2TXEN : inout bit; -- MUX w/GPIO24 N2TXD : inout bit_vector (0 to 3); -- MUX w/GPIO25,26,27,28 N2RXCLK : in bit; N2RXDV : in bit; N2RXD : in bit_vector (0 to 3); N2CRS : in bit; N2COL : in bit; N2MDC : inout bit; N2MDIO : inout bit; I2SDIO : inout bit; -- MUX w/GPIO29 I2SCLK : inout bit; -- MUX w/GPIO30 I2SWRD : inout bit; -- MUX w/GPIO31 TRST_N : in bit; TDI : in bit; TDO : out bit; TMS : in bit; TCK : in bit; TC : in bit_vector (0 to 3); GPIO : inout bit_vector (0 to 15); -- MUX w/SROMCKE, I2SDI, U3CTS, U3DSR, U3DCD, U3RI, U3RTS, U3DTR, IRFIRSEL XTI32 : linkage bit; XTO32 : linkage bit; XTI12 : linkage bit; XTO12 : linkage bit; XPWR12 : linkage bit; XPWR32 : linkage bit; XAGND12 : linkage bit; XAGND32 : linkage bit; RESET_N : in bit; RESET_OUT_N : buffer bit; PWR_EN_N : linkage bit; VDDXOK : in bit; ROMSEL : in bit; ROMSIZ : in bit; TSTEN : in bit; VDDI : linkage bit_vector (0 to 12); VSS : linkage bit_vector (0 to 35); VDDX : linkage bit_vector (0 to 25) ); --- Standard Use Statement (ref B.8.4) --- use STD_1149_1_1994.all; --- Component Conformance Statement (ref B.8.6) --- attribute COMPONENT_CONFORMANCE of AU1000: entity is "STD_1149_1_1993"; --- Device Package Pin Mappings (ref B.8.7) --- attribute PIN_MAP of AU1000 : entity is PHYSICAL_PIN_MAP; constant BGA_22x22 : PIN_MAP_STRING := "SDA: (R22, R21, R20, T22, T21, T20, U22, U21, U20, V22, " & "V21, V20, V19), " & "SDBA: (P21, P20), " & "SDD: (A20, B20, C20, A21, B21, A22, B22, D19, D18, D17, " & "C21, C22, D20, D21, D22, E20, E21, E22, F20, F21, " & "F22, G20, G21, G22, H20, H21, H22, J20, J21, J22, " & "K20, K21), " & "SDQM: (N22, N21, N20, P22), " & "SDRAS_N: M22, " & "SDCAS_N: M20, " & "SDWE_N: L22, " & "SDCLK: (K19, L19, M19), " & "SDCS_N: (K22, L20, L21), " & "SDCKE: M21, " & "RAD: (U4, Y1, V3, W2, U3, W1, V2, T3, V1, U2, " & "R3, U1, T2, T1, R2, P3, R1, P2, N3, P1, " & "N2, N1, M3, M1, M2, L1, L3, L2, K1, K2, " & "K3, J1), " & "RD: (AA10, AB10, AB9, Y9, AA9, AB8, AA8, Y8, AB7, AA7, " & "Y7, AB6, AA6, Y6, AB5, AA5, Y5, AB4, AA4, W5, " & "Y4, AB3, W4, V4, AB2, AA3, Y3, AA2, AB1, AA1, " & "W3, Y2), " & "RBEN_N: (J2, J3, H1, H2), " & "RWE_N: H3, " & "ROE_N: G1, " & "RCE_N: (G2, G3, F1, F2), " & "PREG_N: AB14, " & "PCE_N: (Y12, AB13), " & "POE_N: AA14, " & "PWE_N: Y13, " & "PIOR_N: Y14, " & "PIOW_N: AB16, " & "PWAIT_N: AA13, " & "PIOS16_N: AB15, " & "LCLK: W10, " & "LWAIT_N: AA11, " & "LRD_N: (AA12, Y11), " & "LWR_N: (AB12, Y10), " & "EWAIT_N: AB11, " & "USBHM: B1, " & "USBHP: C3, " & "USBDM: B2, " & "USBDP: D4, " & "S0DOUT: A1, " & "S0DIN: F4, " & "S0CLK: A3, " & "S0DEN: C4, " & "ACSYNC: A5, " & "ACBCLK: B5, " & "ACDO: C8, " & "ACDI: D6, " & "ACRST: C7, " & "IRDATX: E4, " & "IRDARX: C5, " & "U0TXD: A8, " & "U1TXD: B9, " & "U2TXD: A9, " & "U3TXD: C10, " & "U0RXD: D3, " & "U1RXD: B3, " & "U2RXD: A2, " & "U3RXD: D5, " & "N1TXCLK: B4, " & "N1TXEN: A11, " & "N1TXD: (C11, B12, C12, A13), " & "N1RXCLK: B10, " & "N1RXDV: A10, " & "N1RXD: (B6, A6, A7, C9), " & "N1CRS: C6, " & "N1COL: B11, " & "N1MDC: B14, " & "N1MDIO: A16, " & "N2TXCLK: A12, " & "N2TXEN: A18, " & "N2TXD: (B17, C17, C16, A19), " & "N2RXCLK: C15, " & "N2RXDV: B18, " & "N2RXD: (A14, A15, C14, B16), " & "N2CRS: B13, " & "N2COL: C18, " & "N2MDC: B19, " & "N2MDIO: C19, " & "I2SDIO: A4, " & "I2SCLK: B7, " & "I2SWRD: B8, " & "TRST_N: Y22, " & "TDI: D1, " & "TDO: E1, " & "TMS: W20, " & "TCK: C2, " & "TC: (AA18, Y16, AA16, AA15), " & "GPIO: (Y18, AA19, AB18, AA17, AB17, Y15, W14, W13, F3, E2, " & "E3, D2, C1, C13, B15, A17), " & "XTI32: AB21, " & "XTO32: AB22, " & "XTI12: AB19, " & "XTO12: AB20, " & "XPWR12: Y20, " & "XPWR32: AA22, " & "XAGND12: Y19, " & "XAGND32: AA21, " & "RESET_N: AA20, " & "RESET_OUT_N: W22, " & "PWR_EN_N: Y17, " & "VDDXOK: W21, " & "ROMSEL: W19, " & "ROMSIZ: W18, " & "TSTEN: Y21, " & "VDDI: (D10, D11, D12, D13, H19, J19, K4, L4, M4, N19, " & "W9, W11, W12), " & "VSS: (J9, J10, J11, J12, J13, J14, K9, K10, K11, K12, " & "K13, K14, L9, L10, L11, L12, L13, L14, M9, M10, " & "M11, M12, M13, M14, N9, N10, N11, N12, N13, N14, " & "P9, P10, P11, P12, P13, P14), " & "VDDX: (D7, D8, D9, D14, D15, D16, E19, F19, G4, G19, " & "H4, J4, N4, P4, P19, R4, R19, T4, T19, U19, " & "W6, W7, W8, W15, W16, W17)"; --- Scan Port Identification (ref B.8.9) --- attribute TAP_SCAN_CLOCK of TCK : signal is (24.0e6, LOW); -- NOTE: 40MHz is absolute max. -- TCK frequency must always be less than 1/4 system bus frequency. -- 24MHz satisfies default boot frequency. attribute TAP_SCAN_IN of TDI : signal is TRUE; attribute TAP_SCAN_OUT of TDO : signal is TRUE; attribute TAP_SCAN_MODE of TMS : signal is TRUE; attribute TAP_SCAN_RESET of TRST_N : signal is TRUE; --- Instruction Register Description (ref B.8.11) --- attribute INSTRUCTION_LENGTH of AU1000 : entity is 5; attribute INSTRUCTION_OPCODE of AU1000 : entity is "EXTEST (00000)," & "IDCODE (00001)," & "SAMPLE (00010)," & "HIZ (00101)," & "CLAMP (00110)," & "BYPASS (11111)"; attribute INSTRUCTION_CAPTURE of AU1000 : entity is "X0X01"; --- Optional Register Description (ref B.8.12) --- attribute IDCODE_REGISTER of AU1000 : entity is "0000" & -- Version "0000001111101000" & -- Part Number "00101000111" & -- Manufacturer "1"; -- Required by IEEE Std 1149.1-1990 --- Register Access Description (ref B.8.13) --- attribute REGISTER_ACCESS of AU1000 : entity is "BOUNDARY (EXTEST, SAMPLE), " & "BYPASS (BYPASS, HIZ, CLAMP)"; --- Boundary-Scan Register Description (ref B.8.14) --- attribute BOUNDARY_LENGTH of AU1000 : entity is 569; attribute BOUNDARY_REGISTER of AU1000 : entity is "568 (BC_4, GPIO(10), INPUT, x), " & "567 (BC_2, *, control, 0), " & "566 (BC_1, GPIO(10), OUTPUT3, x, 567, 0, Z), " & "565 (BC_4, GPIO(11), INPUT, x), " & "564 (BC_2, *, control, 0), " & "563 (BC_1, GPIO(11), OUTPUT3, x, 564, 0, Z), " & "562 (BC_4, GPIO(12), INPUT, x), " & "561 (BC_2, *, control, 0), " & "560 (BC_1, GPIO(12), OUTPUT3, x, 561, 0, Z), " & "559 (BC_4, S0DIN, INPUT, x), " & "558 (BC_4, U0RXD, INPUT, x), " & "557 (BC_4, S0DOUT, INPUT, x), " & "556 (BC_2, *, control, 0), " & "555 (BC_1, S0DOUT, OUTPUT3, x, 556, 0, Z), " & "554 (BC_4, USBHP, INPUT, x), " & "553 (BC_4, USBHM, INPUT, x), " & "552 (BC_2, *, control, 0), " & "551 (BC_1, USBHM, OUTPUT3, x, 552, 0, Z), " & "550 (BC_1, USBHP, OUTPUT3, x, 552, 0, Z), " & "549 (BC_4, IRDARX, INPUT, x), " & "548 (BC_4, USBDP, INPUT, x), " & "547 (BC_4, USBDM, INPUT, x), " & "546 (BC_2, *, control, 0), " & "545 (BC_1, USBDM, OUTPUT3, x, 546, 0, Z), " & "544 (BC_1, USBDP, OUTPUT3, x, 546, 0, Z), " & "543 (BC_4, U1RXD, INPUT, x), " & "542 (BC_4, U2RXD, INPUT, x), " & "541 (BC_4, U3RXD, INPUT, x), " & "540 (BC_4, S0CLK, INPUT, x), " & "539 (BC_2, *, control, 0), " & "538 (BC_1, S0CLK, OUTPUT3, x, 539, 0, Z), " & "537 (BC_4, S0DEN, INPUT, x), " & "536 (BC_2, *, control, 0), " & "535 (BC_1, S0DEN, OUTPUT3, x, 536, 0, Z), " & "534 (BC_4, ACDI, INPUT, x), " & "533 (BC_4, N1TXCLK, INPUT, x), " & "532 (BC_4, IRDATX, INPUT, x), " & "531 (BC_2, *, control, 0), " & "530 (BC_1, IRDATX, OUTPUT3, x, 531, 0, Z), " & "529 (BC_4, I2SDIO, INPUT, x), " & "528 (BC_2, *, control, 0), " & "527 (BC_1, I2SDIO, OUTPUT3, x, 528, 0, Z), " & "526 (BC_4, N1CRS, INPUT, x), " & "525 (BC_4, ACBCLK, INPUT, x), " & "524 (BC_4, ACRST, INPUT, x), " & "523 (BC_2, *, control, 0), " & "522 (BC_1, ACRST, OUTPUT3, x, 523, 0, Z), " & "521 (BC_4, ACSYNC, INPUT, x), " & "520 (BC_2, *, control, 0), " & "519 (BC_1, ACSYNC, OUTPUT3, x, 520, 0, Z), " & "518 (BC_4, N1RXD(0), INPUT, x), " & "517 (BC_4, N1RXD(1), INPUT, x), " & "516 (BC_4, ACDO, INPUT, x), " & "515 (BC_2, *, control, 0), " & "514 (BC_1, ACDO, OUTPUT3, x, 515, 0, Z), " & "513 (BC_4, I2SCLK, INPUT, x), " & "512 (BC_2, *, control, 0), " & "511 (BC_1, I2SCLK, OUTPUT3, x, 512, 0, Z), " & "510 (BC_4, I2SWRD, INPUT, x), " & "509 (BC_2, *, control, 0), " & "508 (BC_1, I2SWRD, OUTPUT3, x, 509, 0, Z), " & "507 (BC_4, N1RXD(2), INPUT, x), " & "506 (BC_4, N1RXD(3), INPUT, x), " & "505 (BC_4, U0TXD, INPUT, x), " & "504 (BC_2, *, control, 0), " & "503 (BC_1, U0TXD, OUTPUT3, x, 504, 0, Z), " & "502 (BC_4, U1TXD, INPUT, x), " & "501 (BC_2, *, control, 0), " & "500 (BC_1, U1TXD, OUTPUT3, x, 501, 0, Z), " & "499 (BC_4, U2TXD, INPUT, x), " & "498 (BC_2, *, control, 0), " & "497 (BC_1, U2TXD, OUTPUT3, x, 498, 0, Z), " & "496 (BC_4, U3TXD, INPUT, x), " & "495 (BC_2, *, control, 0), " & "494 (BC_1, U3TXD, OUTPUT3, x, 495, 0, Z), " & "493 (BC_4, N1RXCLK, INPUT, x), " & "492 (BC_4, N1RXDV, INPUT, x), " & "491 (BC_4, N1TXEN, INPUT, x), " & "490 (BC_2, *, control, 0), " & "489 (BC_1, N1TXEN, OUTPUT3, x, 490, 0, Z), " & "488 (BC_4, N1TXD(0), INPUT, x), " & "487 (BC_2, *, control, 0), " & "486 (BC_1, N1TXD(0), OUTPUT3, x, 487, 0, Z), " & "485 (BC_4, N1COL, INPUT, x), " & "484 (BC_4, N2TXCLK, INPUT, x), " & "483 (BC_4, N1TXD(1), INPUT, x), " & "482 (BC_2, *, control, 0), " & "481 (BC_1, N1TXD(1), OUTPUT3, x, 482, 0, Z), " & "480 (BC_4, N1TXD(2), INPUT, x), " & "479 (BC_2, *, control, 0), " & "478 (BC_1, N1TXD(2), OUTPUT3, x, 479, 0, Z), " & "477 (BC_4, N1TXD(3), INPUT, x), " & "476 (BC_2, *, control, 0), " & "475 (BC_1, N1TXD(3), OUTPUT3, x, 476, 0, Z), " & "474 (BC_4, N2CRS, INPUT, x), " & "473 (BC_4, N2RXD(0), INPUT, x), " & "472 (BC_4, GPIO(13), INPUT, x), " & "471 (BC_2, *, control, 0), " & "470 (BC_1, GPIO(13), OUTPUT3, x, 471, 0, Z), " & "469 (BC_4, N1MDC, INPUT, x), " & "468 (BC_2, *, control, 0), " & "467 (BC_1, N1MDC, OUTPUT3, x, 468, 0, Z), " & "466 (BC_4, N2RXD(1), INPUT, x), " & "465 (BC_4, N1MDIO, INPUT, x), " & "464 (BC_2, *, control, 0), " & "463 (BC_1, N1MDIO, OUTPUT3, x, 464, 0, Z), " & "462 (BC_4, N2RXD(2), INPUT, x), " & "461 (BC_4, GPIO(14), INPUT, x), " & "460 (BC_2, *, control, 0), " & "459 (BC_1, GPIO(14), OUTPUT3, x, 460, 0, Z), " & "458 (BC_4, GPIO(15), INPUT, x), " & "457 (BC_2, *, control, 0), " & "456 (BC_1, GPIO(15), OUTPUT3, x, 457, 0, Z), " & "455 (BC_4, N2RXD(3), INPUT, x), " & "454 (BC_4, N2RXCLK, INPUT, x), " & "453 (BC_4, N2TXEN, INPUT, x), " & "452 (BC_2, *, control, 0), " & "451 (BC_1, N2TXEN, OUTPUT3, x, 452, 0, Z), " & "450 (BC_4, N2TXD(0), INPUT, x), " & "449 (BC_2, *, control, 0), " & "448 (BC_1, N2TXD(0), OUTPUT3, x, 449, 0, Z), " & "447 (BC_4, N2TXD(1), INPUT, x), " & "446 (BC_2, *, control, 0), " & "445 (BC_1, N2TXD(1), OUTPUT3, x, 446, 0, Z), " & "444 (BC_4, N2TXD(2), INPUT, x), " & "443 (BC_2, *, control, 0), " & "442 (BC_1, N2TXD(2), OUTPUT3, x, 443, 0, Z), " & "441 (BC_4, N2RXDV, INPUT, x), " & "440 (BC_4, N2COL, INPUT, x), " & "439 (BC_4, N2TXD(3), INPUT, x), " & "438 (BC_2, *, control, 0), " & "437 (BC_1, N2TXD(3), OUTPUT3, x, 438, 0, Z), " & "436 (BC_4, N2MDC, INPUT, x), " & "435 (BC_2, *, control, 0), " & "434 (BC_1, N2MDC, OUTPUT3, x, 435, 0, Z), " & "433 (BC_4, N2MDIO, INPUT, x), " & "432 (BC_2, *, control, 0), " & "431 (BC_1, N2MDIO, OUTPUT3, x, 432, 0, Z), " & "430 (BC_4, SDD(0), INPUT, x), " & "429 (BC_2, *, control, 0), " & "428 (BC_1, SDD(0), OUTPUT3, x, 429, 0, Z), " & "427 (BC_4, SDD(1), INPUT, x), " & "426 (BC_2, *, control, 0), " & "425 (BC_1, SDD(1), OUTPUT3, x, 426, 0, Z), " & "424 (BC_4, SDD(2), INPUT, x), " & "423 (BC_2, *, control, 0), " & "422 (BC_1, SDD(2), OUTPUT3, x, 423, 0, Z), " & "421 (BC_4, SDD(3), INPUT, x), " & "420 (BC_2, *, control, 0), " & "419 (BC_1, SDD(3), OUTPUT3, x, 420, 0, Z), " & "418 (BC_4, SDD(4), INPUT, x), " & "417 (BC_2, *, control, 0), " & "416 (BC_1, SDD(4), OUTPUT3, x, 417, 0, Z), " & "415 (BC_4, SDD(5), INPUT, x), " & "414 (BC_2, *, control, 0), " & "413 (BC_1, SDD(5), OUTPUT3, x, 414, 0, Z), " & "412 (BC_4, SDD(6), INPUT, x), " & "411 (BC_2, *, control, 0), " & "410 (BC_1, SDD(6), OUTPUT3, x, 411, 0, Z), " & "409 (BC_4, SDD(7), INPUT, x), " & "408 (BC_2, *, control, 0), " & "407 (BC_1, SDD(7), OUTPUT3, x, 408, 0, Z), " & "406 (BC_4, SDD(8), INPUT, x), " & "405 (BC_2, *, control, 0), " & "404 (BC_1, SDD(8), OUTPUT3, x, 405, 0, Z), " & "403 (BC_4, SDD(9), INPUT, x), " & "402 (BC_2, *, control, 0), " & "401 (BC_1, SDD(9), OUTPUT3, x, 402, 0, Z), " & "400 (BC_4, SDD(10), INPUT, x), " & "399 (BC_2, *, control, 0), " & "398 (BC_1, SDD(10), OUTPUT3, x, 399, 0, Z), " & "397 (BC_4, SDD(11), INPUT, x), " & "396 (BC_2, *, control, 0), " & "395 (BC_1, SDD(11), OUTPUT3, x, 396, 0, Z), " & "394 (BC_4, SDD(12), INPUT, x), " & "393 (BC_2, *, control, 0), " & "392 (BC_1, SDD(12), OUTPUT3, x, 393, 0, Z), " & "391 (BC_4, SDD(13), INPUT, x), " & "390 (BC_2, *, control, 0), " & "389 (BC_1, SDD(13), OUTPUT3, x, 390, 0, Z), " & "388 (BC_4, SDD(14), INPUT, x), " & "387 (BC_2, *, control, 0), " & "386 (BC_1, SDD(14), OUTPUT3, x, 387, 0, Z), " & "385 (BC_4, SDD(15), INPUT, x), " & "384 (BC_2, *, control, 0), " & "383 (BC_1, SDD(15), OUTPUT3, x, 384, 0, Z), " & "382 (BC_4, SDD(16), INPUT, x), " & "381 (BC_2, *, control, 0), " & "380 (BC_1, SDD(16), OUTPUT3, x, 381, 0, Z), " & "379 (BC_4, SDD(17), INPUT, x), " & "378 (BC_2, *, control, 0), " & "377 (BC_1, SDD(17), OUTPUT3, x, 378, 0, Z), " & "376 (BC_4, SDD(18), INPUT, x), " & "375 (BC_2, *, control, 0), " & "374 (BC_1, SDD(18), OUTPUT3, x, 375, 0, Z), " & "373 (BC_4, SDD(19), INPUT, x), " & "372 (BC_2, *, control, 0), " & "371 (BC_1, SDD(19), OUTPUT3, x, 372, 0, Z), " & "370 (BC_4, SDD(20), INPUT, x), " & "369 (BC_2, *, control, 0), " & "368 (BC_1, SDD(20), OUTPUT3, x, 369, 0, Z), " & "367 (BC_4, SDD(21), INPUT, x), " & "366 (BC_2, *, control, 0), " & "365 (BC_1, SDD(21), OUTPUT3, x, 366, 0, Z), " & "364 (BC_4, SDD(22), INPUT, x), " & "363 (BC_2, *, control, 0), " & "362 (BC_1, SDD(22), OUTPUT3, x, 363, 0, Z), " & "361 (BC_4, SDD(23), INPUT, x), " & "360 (BC_2, *, control, 0), " & "359 (BC_1, SDD(23), OUTPUT3, x, 360, 0, Z), " & "358 (BC_4, SDD(24), INPUT, x), " & "357 (BC_2, *, control, 0), " & "356 (BC_1, SDD(24), OUTPUT3, x, 357, 0, Z), " & "355 (BC_4, SDD(25), INPUT, x), " & "354 (BC_2, *, control, 0), " & "353 (BC_1, SDD(25), OUTPUT3, x, 354, 0, Z), " & "352 (BC_4, SDD(26), INPUT, x), " & "351 (BC_2, *, control, 0), " & "350 (BC_1, SDD(26), OUTPUT3, x, 351, 0, Z), " & "349 (BC_4, SDD(27), INPUT, x), " & "348 (BC_2, *, control, 0), " & "347 (BC_1, SDD(27), OUTPUT3, x, 348, 0, Z), " & "346 (BC_4, SDD(28), INPUT, x), " & "345 (BC_2, *, control, 0), " & "344 (BC_1, SDD(28), OUTPUT3, x, 345, 0, Z), " & "343 (BC_4, SDD(29), INPUT, x), " & "342 (BC_2, *, control, 0), " & "341 (BC_1, SDD(29), OUTPUT3, x, 342, 0, Z), " & "340 (BC_4, SDD(30), INPUT, x), " & "339 (BC_2, *, control, 0), " & "338 (BC_1, SDD(30), OUTPUT3, x, 339, 0, Z), " & "337 (BC_4, SDD(31), INPUT, x), " & "336 (BC_2, *, control, 0), " & "335 (BC_1, SDD(31), OUTPUT3, x, 336, 0, Z), " & "334 (BC_1, SDCS_N(0), OUTPUT2, x), " & "333 (BC_1, *, internal, x), " & "332 (BC_2, *, control, 0), " & "331 (BC_1, SDCLK(0), OUTPUT3, x, 332, 0, Z), " & "330 (BC_1, SDCS_N(1), OUTPUT2, x), " & "329 (BC_1, SDCS_N(2), OUTPUT2, x), " & "328 (BC_1, SDWE_N, OUTPUT2, x), " & "327 (BC_1, *, internal, x), " & "326 (BC_2, *, control, 0), " & "325 (BC_1, SDCLK(1), OUTPUT3, x, 326, 0, Z), " & "324 (BC_1, SDRAS_N, OUTPUT2, x), " & "323 (BC_1, SDCKE, OUTPUT2, x), " & "322 (BC_1, SDCAS_N, OUTPUT2, x), " & "321 (BC_1, *, internal, x), " & "320 (BC_2, *, control, 0), " & "319 (BC_1, SDCLK(2), OUTPUT3, x, 320, 0, Z), " & "318 (BC_1, SDQM(0), OUTPUT2, x), " & "317 (BC_1, SDQM(1), OUTPUT2, x), " & "316 (BC_1, SDQM(2), OUTPUT2, x), " & "315 (BC_1, SDQM(3), OUTPUT2, x), " & "314 (BC_1, SDBA(0), OUTPUT2, x), " & "313 (BC_1, SDBA(1), OUTPUT2, x), " & "312 (BC_1, SDA(0), OUTPUT2, x), " & "311 (BC_1, SDA(1), OUTPUT2, x), " & "310 (BC_1, SDA(2), OUTPUT2, x), " & "309 (BC_1, SDA(3), OUTPUT2, x), " & "308 (BC_1, SDA(4), OUTPUT2, x), " & "307 (BC_1, SDA(5), OUTPUT2, x), " & "306 (BC_1, SDA(6), OUTPUT2, x), " & "305 (BC_1, SDA(7), OUTPUT2, x), " & "304 (BC_1, SDA(8), OUTPUT2, x), " & "303 (BC_1, SDA(9), OUTPUT2, x), " & "302 (BC_1, SDA(10), OUTPUT2, x), " & "301 (BC_1, SDA(11), OUTPUT2, x), " & "300 (BC_1, SDA(12), OUTPUT2, x), " & "299 (BC_1, RESET_OUT_N, OUTPUT2, x), " & "298 (BC_4, VDDXOK, INPUT, x), " & "297 (BC_4, TSTEN, INPUT, x), " & "296 (BC_4, ROMSEL, INPUT, x), " & "295 (BC_4, ROMSIZ, INPUT, x), " & "294 (BC_4, RESET_N, INPUT, x), " & "293 (BC_4, GPIO(0), INPUT, x), " & "292 (BC_2, *, control, 0), " & "291 (BC_1, GPIO(0), OUTPUT3, x, 292, 0, Z), " & "290 (BC_4, GPIO(1), INPUT, x), " & "289 (BC_2, *, control, 0), " & "288 (BC_1, GPIO(1), OUTPUT3, x, 289, 0, Z), " & "287 (BC_4, TC(0), INPUT, x), " & "286 (BC_4, TC(1), INPUT, x), " & "285 (BC_4, GPIO(2), INPUT, x), " & "284 (BC_2, *, control, 0), " & "283 (BC_1, GPIO(2), OUTPUT3, x, 284, 0, Z), " & "282 (BC_4, GPIO(3), INPUT, x), " & "281 (BC_2, *, control, 0), " & "280 (BC_1, GPIO(3), OUTPUT3, x, 281, 0, Z), " & "279 (BC_4, GPIO(4), INPUT, x), " & "278 (BC_2, *, control, 0), " & "277 (BC_1, GPIO(4), OUTPUT3, x, 278, 0, Z), " & "276 (BC_4, GPIO(5), INPUT, x), " & "275 (BC_2, *, control, 0), " & "274 (BC_1, GPIO(5), OUTPUT3, x, 275, 0, Z), " & "273 (BC_4, GPIO(6), INPUT, x), " & "272 (BC_2, *, control, 0), " & "271 (BC_1, GPIO(6), OUTPUT3, x, 272, 0, Z), " & "270 (BC_4, TC(2), INPUT, x), " & "269 (BC_4, TC(3), INPUT, x), " & "268 (BC_4, GPIO(7), INPUT, x), " & "267 (BC_2, *, control, 0), " & "266 (BC_1, GPIO(7), OUTPUT3, x, 267, 0, Z), " & "265 (BC_4, PIOW_N, INPUT, x), " & "264 (BC_2, *, control, 0), " & "263 (BC_1, PIOW_N, OUTPUT3, x, 264, 0, Z), " & "262 (BC_4, PIOR_N, INPUT, x), " & "261 (BC_2, *, control, 0), " & "260 (BC_1, PIOR_N, OUTPUT3, x, 261, 0, Z), " & "259 (BC_4, PIOS16_N, INPUT, x), " & "258 (BC_4, PWE_N, INPUT, x), " & "257 (BC_2, *, control, 0), " & "256 (BC_1, PWE_N, OUTPUT3, x, 257, 0, Z), " & "255 (BC_4, POE_N, INPUT, x), " & "254 (BC_2, *, control, 0), " & "253 (BC_1, POE_N, OUTPUT3, x, 254, 0, Z), " & "252 (BC_4, PREG_N, INPUT, x), " & "251 (BC_2, *, control, 0), " & "250 (BC_1, PREG_N, OUTPUT3, x, 251, 0, Z), " & "249 (BC_4, PWAIT_N, INPUT, x), " & "248 (BC_4, PCE_N(0), INPUT, x), " & "247 (BC_2, *, control, 0), " & "246 (BC_1, PCE_N(0), OUTPUT3, x, 247, 0, Z), " & "245 (BC_4, PCE_N(1), INPUT, x), " & "244 (BC_2, *, control, 0), " & "243 (BC_1, PCE_N(1), OUTPUT3, x, 244, 0, Z), " & "242 (BC_4, LRD_N(0), INPUT, x), " & "241 (BC_2, *, control, 0), " & "240 (BC_1, LRD_N(0), OUTPUT3, x, 241, 0, Z), " & "239 (BC_4, LRD_N(1), INPUT, x), " & "238 (BC_2, *, control, 0), " & "237 (BC_1, LRD_N(1), OUTPUT3, x, 238, 0, Z), " & "236 (BC_4, LWR_N(0), INPUT, x), " & "235 (BC_2, *, control, 0), " & "234 (BC_1, LWR_N(0), OUTPUT3, x, 235, 0, Z), " & "233 (BC_4, LWAIT_N, INPUT, x), " & "232 (BC_4, EWAIT_N, INPUT, x), " & "231 (BC_1, LCLK, OUTPUT2, x), " & "230 (BC_4, LWR_N(1), INPUT, x), " & "229 (BC_2, *, control, 0), " & "228 (BC_1, LWR_N(1), OUTPUT3, x, 229, 0, Z), " & "227 (BC_4, RD(0), INPUT, x), " & "226 (BC_2, *, control, 0), " & "225 (BC_1, RD(0), OUTPUT3, x, 226, 0, Z), " & "224 (BC_4, RD(1), INPUT, x), " & "223 (BC_2, *, control, 0), " & "222 (BC_1, RD(1), OUTPUT3, x, 223, 0, Z), " & "221 (BC_4, RD(2), INPUT, x), " & "220 (BC_2, *, control, 0), " & "219 (BC_1, RD(2), OUTPUT3, x, 220, 0, Z), " & "218 (BC_4, RD(3), INPUT, x), " & "217 (BC_2, *, control, 0), " & "216 (BC_1, RD(3), OUTPUT3, x, 217, 0, Z), " & "215 (BC_4, RD(4), INPUT, x), " & "214 (BC_2, *, control, 0), " & "213 (BC_1, RD(4), OUTPUT3, x, 214, 0, Z), " & "212 (BC_4, RD(5), INPUT, x), " & "211 (BC_2, *, control, 0), " & "210 (BC_1, RD(5), OUTPUT3, x, 211, 0, Z), " & "209 (BC_4, RD(6), INPUT, x), " & "208 (BC_2, *, control, 0), " & "207 (BC_1, RD(6), OUTPUT3, x, 208, 0, Z), " & "206 (BC_4, RD(7), INPUT, x), " & "205 (BC_2, *, control, 0), " & "204 (BC_1, RD(7), OUTPUT3, x, 205, 0, Z), " & "203 (BC_4, RD(8), INPUT, x), " & "202 (BC_2, *, control, 0), " & "201 (BC_1, RD(8), OUTPUT3, x, 202, 0, Z), " & "200 (BC_4, RD(9), INPUT, x), " & "199 (BC_2, *, control, 0), " & "198 (BC_1, RD(9), OUTPUT3, x, 199, 0, Z), " & "197 (BC_4, RD(10), INPUT, x), " & "196 (BC_2, *, control, 0), " & "195 (BC_1, RD(10), OUTPUT3, x, 196, 0, Z), " & "194 (BC_4, RD(11), INPUT, x), " & "193 (BC_2, *, control, 0), " & "192 (BC_1, RD(11), OUTPUT3, x, 193, 0, Z), " & "191 (BC_4, RD(12), INPUT, x), " & "190 (BC_2, *, control, 0), " & "189 (BC_1, RD(12), OUTPUT3, x, 190, 0, Z), " & "188 (BC_4, RD(13), INPUT, x), " & "187 (BC_2, *, control, 0), " & "186 (BC_1, RD(13), OUTPUT3, x, 187, 0, Z), " & "185 (BC_4, RD(14), INPUT, x), " & "184 (BC_2, *, control, 0), " & "183 (BC_1, RD(14), OUTPUT3, x, 184, 0, Z), " & "182 (BC_4, RD(15), INPUT, x), " & "181 (BC_2, *, control, 0), " & "180 (BC_1, RD(15), OUTPUT3, x, 181, 0, Z), " & "179 (BC_4, RD(16), INPUT, x), " & "178 (BC_2, *, control, 0), " & "177 (BC_1, RD(16), OUTPUT3, x, 178, 0, Z), " & "176 (BC_4, RD(17), INPUT, x), " & "175 (BC_2, *, control, 0), " & "174 (BC_1, RD(17), OUTPUT3, x, 175, 0, Z), " & "173 (BC_4, RD(18), INPUT, x), " & "172 (BC_2, *, control, 0), " & "171 (BC_1, RD(18), OUTPUT3, x, 172, 0, Z), " & "170 (BC_4, RD(19), INPUT, x), " & "169 (BC_2, *, control, 0), " & "168 (BC_1, RD(19), OUTPUT3, x, 169, 0, Z), " & "167 (BC_4, RD(20), INPUT, x), " & "166 (BC_2, *, control, 0), " & "165 (BC_1, RD(20), OUTPUT3, x, 166, 0, Z), " & "164 (BC_4, RD(21), INPUT, x), " & "163 (BC_2, *, control, 0), " & "162 (BC_1, RD(21), OUTPUT3, x, 163, 0, Z), " & "161 (BC_4, RD(22), INPUT, x), " & "160 (BC_2, *, control, 0), " & "159 (BC_1, RD(22), OUTPUT3, x, 160, 0, Z), " & "158 (BC_4, RD(23), INPUT, x), " & "157 (BC_2, *, control, 0), " & "156 (BC_1, RD(23), OUTPUT3, x, 157, 0, Z), " & "155 (BC_4, RD(24), INPUT, x), " & "154 (BC_2, *, control, 0), " & "153 (BC_1, RD(24), OUTPUT3, x, 154, 0, Z), " & "152 (BC_4, RD(25), INPUT, x), " & "151 (BC_2, *, control, 0), " & "150 (BC_1, RD(25), OUTPUT3, x, 151, 0, Z), " & "149 (BC_4, RD(26), INPUT, x), " & "148 (BC_2, *, control, 0), " & "147 (BC_1, RD(26), OUTPUT3, x, 148, 0, Z), " & "146 (BC_4, RD(27), INPUT, x), " & "145 (BC_2, *, control, 0), " & "144 (BC_1, RD(27), OUTPUT3, x, 145, 0, Z), " & "143 (BC_4, RD(28), INPUT, x), " & "142 (BC_2, *, control, 0), " & "141 (BC_1, RD(28), OUTPUT3, x, 142, 0, Z), " & "140 (BC_4, RD(29), INPUT, x), " & "139 (BC_2, *, control, 0), " & "138 (BC_1, RD(29), OUTPUT3, x, 139, 0, Z), " & "137 (BC_4, RD(30), INPUT, x), " & "136 (BC_2, *, control, 0), " & "135 (BC_1, RD(30), OUTPUT3, x, 136, 0, Z), " & "134 (BC_4, RD(31), INPUT, x), " & "133 (BC_2, *, control, 0), " & "132 (BC_1, RD(31), OUTPUT3, x, 133, 0, Z), " & "131 (BC_4, RAD(0), INPUT, x), " & "130 (BC_2, *, control, 0), " & "129 (BC_1, RAD(0), OUTPUT3, x, 130, 0, Z), " & "128 (BC_4, RAD(1), INPUT, x), " & "127 (BC_2, *, control, 0), " & "126 (BC_1, RAD(1), OUTPUT3, x, 127, 0, Z), " & "125 (BC_4, RAD(2), INPUT, x), " & "124 (BC_2, *, control, 0), " & "123 (BC_1, RAD(2), OUTPUT3, x, 124, 0, Z), " & "122 (BC_4, RAD(3), INPUT, x), " & "121 (BC_2, *, control, 0), " & "120 (BC_1, RAD(3), OUTPUT3, x, 121, 0, Z), " & "119 (BC_4, RAD(4), INPUT, x), " & "118 (BC_2, *, control, 0), " & "117 (BC_1, RAD(4), OUTPUT3, x, 118, 0, Z), " & "116 (BC_4, RAD(5), INPUT, x), " & "115 (BC_2, *, control, 0), " & "114 (BC_1, RAD(5), OUTPUT3, x, 115, 0, Z), " & "113 (BC_4, RAD(6), INPUT, x), " & "112 (BC_2, *, control, 0), " & "111 (BC_1, RAD(6), OUTPUT3, x, 112, 0, Z), " & "110 (BC_4, RAD(7), INPUT, x), " & "109 (BC_2, *, control, 0), " & "108 (BC_1, RAD(7), OUTPUT3, x, 109, 0, Z), " & "107 (BC_4, RAD(8), INPUT, x), " & "106 (BC_2, *, control, 0), " & "105 (BC_1, RAD(8), OUTPUT3, x, 106, 0, Z), " & "104 (BC_4, RAD(9), INPUT, x), " & "103 (BC_2, *, control, 0), " & "102 (BC_1, RAD(9), OUTPUT3, x, 103, 0, Z), " & "101 (BC_4, RAD(10), INPUT, x), " & "100 (BC_2, *, control, 0), " & "99 (BC_1, RAD(10), OUTPUT3, x, 100, 0, Z), " & "98 (BC_4, RAD(11), INPUT, x), " & "97 (BC_2, *, control, 0), " & "96 (BC_1, RAD(11), OUTPUT3, x, 97, 0, Z), " & "95 (BC_4, RAD(12), INPUT, x), " & "94 (BC_2, *, control, 0), " & "93 (BC_1, RAD(12), OUTPUT3, x, 94, 0, Z), " & "92 (BC_4, RAD(13), INPUT, x), " & "91 (BC_2, *, control, 0), " & "90 (BC_1, RAD(13), OUTPUT3, x, 91, 0, Z), " & "89 (BC_4, RAD(14), INPUT, x), " & "88 (BC_2, *, control, 0), " & "87 (BC_1, RAD(14), OUTPUT3, x, 88, 0, Z), " & "86 (BC_4, RAD(15), INPUT, x), " & "85 (BC_2, *, control, 0), " & "84 (BC_1, RAD(15), OUTPUT3, x, 85, 0, Z), " & "83 (BC_4, RAD(16), INPUT, x), " & "82 (BC_2, *, control, 0), " & "81 (BC_1, RAD(16), OUTPUT3, x, 82, 0, Z), " & "80 (BC_4, RAD(17), INPUT, x), " & "79 (BC_2, *, control, 0), " & "78 (BC_1, RAD(17), OUTPUT3, x, 79, 0, Z), " & "77 (BC_4, RAD(18), INPUT, x), " & "76 (BC_2, *, control, 0), " & "75 (BC_1, RAD(18), OUTPUT3, x, 76, 0, Z), " & "74 (BC_4, RAD(19), INPUT, x), " & "73 (BC_2, *, control, 0), " & "72 (BC_1, RAD(19), OUTPUT3, x, 73, 0, Z), " & "71 (BC_4, RAD(20), INPUT, x), " & "70 (BC_2, *, control, 0), " & "69 (BC_1, RAD(20), OUTPUT3, x, 70, 0, Z), " & "68 (BC_4, RAD(21), INPUT, x), " & "67 (BC_2, *, control, 0), " & "66 (BC_1, RAD(21), OUTPUT3, x, 67, 0, Z), " & "65 (BC_4, RAD(22), INPUT, x), " & "64 (BC_2, *, control, 0), " & "63 (BC_1, RAD(22), OUTPUT3, x, 64, 0, Z), " & "62 (BC_4, RAD(23), INPUT, x), " & "61 (BC_2, *, control, 0), " & "60 (BC_1, RAD(23), OUTPUT3, x, 61, 0, Z), " & "59 (BC_4, RAD(24), INPUT, x), " & "58 (BC_2, *, control, 0), " & "57 (BC_1, RAD(24), OUTPUT3, x, 58, 0, Z), " & "56 (BC_4, RAD(25), INPUT, x), " & "55 (BC_2, *, control, 0), " & "54 (BC_1, RAD(25), OUTPUT3, x, 55, 0, Z), " & "53 (BC_4, RAD(26), INPUT, x), " & "52 (BC_2, *, control, 0), " & "51 (BC_1, RAD(26), OUTPUT3, x, 52, 0, Z), " & "50 (BC_4, RAD(27), INPUT, x), " & "49 (BC_2, *, control, 0), " & "48 (BC_1, RAD(27), OUTPUT3, x, 49, 0, Z), " & "47 (BC_4, RAD(28), INPUT, x), " & "46 (BC_2, *, control, 0), " & "45 (BC_1, RAD(28), OUTPUT3, x, 46, 0, Z), " & "44 (BC_4, RAD(29), INPUT, x), " & "43 (BC_2, *, control, 0), " & "42 (BC_1, RAD(29), OUTPUT3, x, 43, 0, Z), " & "41 (BC_4, RAD(30), INPUT, x), " & "40 (BC_2, *, control, 0), " & "39 (BC_1, RAD(30), OUTPUT3, x, 40, 0, Z), " & "38 (BC_4, RAD(31), INPUT, x), " & "37 (BC_2, *, control, 0), " & "36 (BC_1, RAD(31), OUTPUT3, x, 37, 0, Z), " & "35 (BC_4, RBEN_N(0), INPUT, x), " & "34 (BC_2, *, control, 0), " & "33 (BC_1, RBEN_N(0), OUTPUT3, x, 34, 0, Z), " & "32 (BC_4, RBEN_N(1), INPUT, x), " & "31 (BC_2, *, control, 0), " & "30 (BC_1, RBEN_N(1), OUTPUT3, x, 31, 0, Z), " & "29 (BC_4, RBEN_N(2), INPUT, x), " & "28 (BC_2, *, control, 0), " & "27 (BC_1, RBEN_N(2), OUTPUT3, x, 28, 0, Z), " & "26 (BC_4, RBEN_N(3), INPUT, x), " & "25 (BC_2, *, control, 0), " & "24 (BC_1, RBEN_N(3), OUTPUT3, x, 25, 0, Z), " & "23 (BC_4, RWE_N, INPUT, x), " & "22 (BC_2, *, control, 0), " & "21 (BC_1, RWE_N, OUTPUT3, x, 22, 0, Z), " & "20 (BC_4, ROE_N, INPUT, x), " & "19 (BC_2, *, control, 0), " & "18 (BC_1, ROE_N, OUTPUT3, x, 19, 0, Z), " & "17 (BC_4, RCE_N(0), INPUT, x), " & "16 (BC_2, *, control, 0), " & "15 (BC_1, RCE_N(0), OUTPUT3, x, 16, 0, Z), " & "14 (BC_4, RCE_N(1), INPUT, x), " & "13 (BC_2, *, control, 0), " & "12 (BC_1, RCE_N(1), OUTPUT3, x, 13, 0, Z), " & "11 (BC_4, RCE_N(2), INPUT, x), " & "10 (BC_2, *, control, 0), " & "9 (BC_1, RCE_N(2), OUTPUT3, x, 10, 0, Z), " & "8 (BC_4, RCE_N(3), INPUT, x), " & "7 (BC_2, *, control, 0), " & "6 (BC_1, RCE_N(3), OUTPUT3, x, 7, 0, Z), " & "5 (BC_4, GPIO(8), INPUT, x), " & "4 (BC_2, *, control, 0), " & "3 (BC_1, GPIO(8), OUTPUT3, x, 4, 0, Z), " & "2 (BC_4, GPIO(9), INPUT, x), " & "1 (BC_2, *, control, 0), " & "0 (BC_1, GPIO(9), OUTPUT3, x, 1, 0, Z) "; end AU1000;