RMI Alchemy™ Solutions Au1100® Processor Family
Internet Edge Processor
A High-Performance/Low-Power MIPS® (SoC) with LCD Controller
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Overview
The RMI Alchemy™ Solutions Au1100® processor, a follow-on to
the RMI Alchemy™ Solutions Au1000™ processor, provides a high-performance,
low-power, high-integration System-on-a-Chip (SoC) with the inclusion of
a LCD controller and further reduction in power over the Au1000 processor.
The Au1100 processor targets Mobile Information Appliances (IAs). These
IAs include Web pads, telematics, PDAs, and multimedia handheld computing
devices.
Product Description
The Au1100 processor delivers a complete SoC based on the MIPS32®
instruction set. Designed for optimal performance at a very low power, the
Au1100 processor is available up to 500MHz. Power dissipation measures less than 0.25
watt for the 400MHz version. It features highly-integrated technology including
on-chip SDRAM, SRAM/Flash EPROM memory controllers, an LCD controller, 10/100
Ethernet Controller, USB Host and Device, UARTs (3), and GPIOs (up to 48,
13 dedicated). In addition, the incorporation of peripherals with this very
high-performance, MIPS-compatible core can provide lower system costs, smaller
form factors, lower system power requirements, simpler designs at multiple
performance points, and shorter design cycles.
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High-Speed MIPS
CPU Core
- 333, 400 or 500MHz
- MIPS32® Instruction Set
- 32-Bit Architecture
- 16KB Instruction and 16KB Data Caches
- High Speed Multiply-Accumulate (MAC) and Divide Unit
- 1.1-1.3V Core, 2.5/3.3V I/O
Highly-Integrated System Peripherals
- GPIO (48 total, 13 dedicated for system use)
- 10/100 Ethernet Controller
- USB Device and Host Controller
- Three UARTs
- IrDA Controller
- AC-97 Controller
- I2S Controller
- Two Secure Digital (SD) Controllers
- Two SSI Controllers
- LCD Controller
- PCMCIA Interface Controller
On-Chip LCD Controller
- Single and Dual Panel Color
- TFT and STN Displays
- Up to 640x480 or 800x600 at 16bpp
- Supported through Unified SDRAM-Based Frame Buffer
- Hardware Rotate for Portrait-vs-Landscape (90°, 180°, 270°,
up to 320x240)
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High Bandwith
Memory Buses
- 100/125MHz SDRAM Controller
- SRAM/Flash EPROM Controller
Low System Power
| Core MHz |
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Power(mW) |
| 333 |
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<200 |
| 400 |
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250 |
| 500 |
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500 |
- Power-saving Modes
- Pseudo-static Design to 0Hz
Package
Operating System Support
- Microsoft® Windows® CE.NET
- Linux
- VxWorks
Development Tool Support
- MIPS32-compatible Tool Set
- Numerous Third-Party Compilers, Assemblers and Debuggers
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| Processor Diagram |
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Core Microarchitecture
Highlights Pipeline
- Scalar 5-stage Pipeline
- Load/Store Adder in 1-stage
- Scalar Branch Techniques Optimized
- Pipelined Register File Access in Fetch Stage
- Zero Penalty Branch
Multiply-Accumulate (MAC) and Divide Unit
- Max Issue Rate of one 32x16 MAC per Clock
- Max Issues Rate of one 32x32 MAC per Every Other Clock
- Operates in Parallel to CPU Pipeline
- Executes all Integer Multiply and Divide Instructions
- 32 x 16-bit MAC Hardware
MMU
- Instruction and Data Watch Registers for Software Breakpoints
- Separate Interrupt Exception Vector
- TLB
- 32 Dual-entry, Fully Associative
- Variable Page Sizes 4KB-16MB
- 4-entry ITB
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Caches
- 16KB Non-Blocking Data Cache
- 16KB Instruction Cache
- Instruction/Data Caches are 4-Way Set Associative
- Write-Back with Read-Allocate
- Cache-management Features
- Programmable Allocation Policy
- Line Locking
- Prefetch Instructions (instructions and data)
- High-speed Access to On-chip Buses
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the PDF |
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