Silicon Advantage

RMI’s advanced processors can deliver functionality, performance and cost that differentiate us from competitors across a broad range of markets and applications. We believe we accomplish this by tight integration of key technologies and an innovative architecture, including our power-optimized processor core and SoC design, our thread processing technology, our on-chip fast messaging network, and the integration of various acceleration and security engines including; autonomous networking acceleration engine, security encryption engines, compression/decompression engines and the media acceleration engine. The following elements are the key technologies and architectural features of our processor solutions.

• Very Low Power Processor Core and SoC Design

• Thread Processor Technology

• Fast Messaging Network Technology

• Autonomous Networking Accelerators and Security and
  Compression Engines

Autonomous Networking Accelerators and Security and Compression Engines

As more and more processing requirements are placed on SoCs, efficient processor resource sharing becomes a significant performance challenge. This results in ineffective workload distribution and management.  Many of today’s multiprocessors utilize a standard direct memory access (“DMA”) ring in which all CPU resources will attempt to access a single data structure.  This is extremely inefficient since it frequently requires the use of data locks, thus consuming an unusually large percentage of CPU time simply to access the data without completing any meaningful work.  It is also not uncommon for a subset of processor resources, which could have been used for more productive output, to be dedicated simply to manage the workload distribution burden.  In either case, throughput potential is wasted.  To address this issue, our SoC processors are equipped with highly optimized acceleration engines that offload the processor cores and streamline processing efficiency.

Our Networking Accelerator supports higher-layer programmable parsing, packet direction management, checksum verification and load balanced packet distribution across the multiple processor threads. Our proprietary Autonomous Security Acceleration EngineTM completely off-loads encryption/decryption and authentication-related hashing operations from the central processing cores, enables up to 10 Gbps of bulk cryptographic processing and supports industry standard security protocols such as IPsec and security sockets layer (“SSL”).

Our autonomous on-chip Advanced Encryption Standard (AES) Cryptography Engine for both our Alchemy media and control plane processors, supports 128-bit AES in ECB, CBC, CFB and OFB modes, and uses the data transfer capabilities of a DBDMA Controller to augment the encryption/decryption functions. Decryption functionality implemented in on-chip hardware enables device manufacturers to avoid slowing down the processor with the security function and frees up processing power for other device requirements. For control plane applications, our security engine supports virtual private network (VPN) solutions for both IPsec and SSL, allowing designers the flexibility in selecting security configurations and performance options.

Our Autonomous Compression/Decompression Engine offloads the compression functions to an autonomous IP block, freeing up additional processing capacity within each core for greater efficiency and throughput.

For more information, view the XLR Processor and XLS Processor Overviews